• ASIC architecture and specification generation for multi-million gate implementations.
• Marketing requirement document generation (with assistance from internal marketing personnel)
• Methodology development and implementation.
• ASIC behavioral & RTL design in VHDL or Verilog.
• Behavioral & RTL simulation and verification.
• Physical Synthesis and Floor-planning.
• Synthesis script generation & debug.
• Gate level timing analysis script generation & debug.
• Post-route timing verification.
• Verification environment and Functional test set creation.
• DFT insertion.
• Formal design verification.
• CMOS Gate arrays/Standard cell, FPGA.
• Design for radiation environment, including SEU tolerance.
• Model Technology’s compilers and simulators for VHDL, Verilog and SystemVerilog.
• Synopsys Physical Compiler, Design Compiler and PrimeTime tools.
• Synplicity FPGA synthesis tool.
• Cadence Verilog HDL.
• New methodology and verification environment for telephony FPGA verification.
• Redesign configurable IP blocks for resource efficiency and performance.
• Library test chip for deep sub-micron specialized IO testing.
• ATE Next Generation Tester Chipset. (4M gate design implemented in 2 ASICs)
• AGP 4X Master interface logic. (Used in 6M+ gate graphics ASIC)
• Limited PCI to PCI/AGP bridge.
• PCI 3D Graphics controller, including VGA logic. (Used in 6M+ gate graphics ASIC)
• PCI configurable/parameterized interface logic macro in VHDL.
• Multi-function parallel port controller logic. (ECP+EPP+STD)
• VME interface to satellite RF logic.
• FPGA based UART for space application.
• IO Interfacing FPGA for hostile environment application.
• Navigation sensor FPGA for hostile environment application.