North Dakota State University-CNSE ***** Fargo, ND
Senior Design/Packaging Engineer
• Design & ***** Experience
o High Speed LAN, 10MBPs/100MBPs
o Host USB at 480MBPs
o PCI Buses
o DDR 133MHz Buses
o Multiple ASICS on the PCI bus
o High Speed routing
o CES setup
o Auto-routing setup and tuning for DDR2
o Working knowledge of Aerospace, Military and commercial standards
• Trouble Shooting and resolving of board level issues
• Design of Chip Scale Packages & associated Tooling
• Mentored & trained students on how to design Printed Circuit Boards and Chip Scale Packages

Micron Technology, Inc. Boise, ID
Senior Design/Packaging Engineer 1996 to 2003
• Directed the first design and modeling of the Through Silicon Via, TSV concepts
• Directed the effort with a foreign company set standard grids for DDR1 x8 and x4 module configurations.
• Facilitated second source for memory that would work on existing modules
• Reduced overhead by 25% by re-distributing wire bond pads and layers on after-market chip designs
• Designed DIMM and SIMM modules for testing metallurgical interconnects
• Understands Saw, Die Attach, Wire Bonding, Molding, Encapsulation and Trim & Form
• Designed flexible circuits, thin low pin count, ultra-thin high pin count BGAs Chip Scale Packages
• Designed MEMS using VeriBest Suite to determine route ability of electrical connections

Senior Process Engineer 1990 to 1996
• Participated on a development team that found a new test methodology to create Known Good Die, KGD.
• Directed the development and implementation of KGD Vision and calibration
• Saved $5 Million Dollars a quarter in revenue by optimizing the final passivation
• Saved $2 Million a quarter by setting up an offshore assembly area in Europe
• Wrote 81 and received 28 patents

Arizona State University
Tempe, AZ
Bachelor of Science 1972
Electronic Technology

Continuing Professional Education:
• Demystifying High Speed PCB Design, Dr. Douglas Brooks; Year 1998
• Grounding Shielding of Electronic Systems, National Technical University, Dr. Van Doren; Year 1998
• FPGA Desktop Simulation / VHDL, VeriBest, Inc. Leroy Riggs; Year 1998
• High Speed PCB Design, Dr. Lee Ritchie; Year 2001

• Laid out components and designed traces to meet Impedance controlled RF circuits to 3 GHz
• Designed computer mother boards with two processors & DDR tuned memory
• Designed RF sensor boards to detect a variety of Gases using RF Technology
• Designed a test board for evaluating a Micro-processor with Impedance controlled signal traces
• Designed boards with 18 conductive multi-layers with Impedance controlled traces.
• Designed, setup and ran three assembly areas offshore to support marketing strategies
• Lead design and test teams to collaboratively meet sales and marketing objectives
• Traveled extensively in Southeast Asia and England to deal with Packaging Subcontractors
• Detailed information and design techniques for MAP tooling
• Designed 11 Chip Scale Packages, including Chip & Wire as well as Flip Chip interconnects
• Designed a RDL Flip Chip version of RAMBUS memory Chip
• Certified Chip Scale Multilayer Laminate Organic Substrate and Tooling Designer from Tessera
• Designs substrates to meet or exceed electrical performance of the I.C.
• Directed initial TSV electrical modeling at Micron Technology
• Worked with Aerospace companies for 6 years laying out RF, Analog and Digital PCB’s
• GD&T ASME Y14.5 understood and used
• Uses a systematic guideline sheet to ***** PCB’s
• Familiar with Hierarchal Schematic blocks for wiring and *****