We have a problem of debugging a piece of program running on a custom made xilinx virtex 6 fpga board. This problem related to access external ddr3 sodimm sdram. We need an xilinx fpga export to help solve this problem. Problem details as follows:
memory interface problems
a program running on a virtex 6 fpga writes eight sequential data patterns (0 to 511) into different
address ranges of an external ddr3 sodimm (“write cycle”). The data pattern and addresses are
designed in such way that the lower 9 bits of the data and address match.
After all data is written, the data is read back (“read cycle”) in a different order and the least 9 bits of
address and data are compared.
The core to interface with the sodimm was generated with xilinx mig-tool v3.92.
using chipscope the data and address written into and received from the memory interface is
the data and address written into the memory interface are correct every time. The data and address
match from the beginning to the end of each write cycle.
at the beginning of the first read cycle the data read from the memory interface is correct. After about
1920 consecutive read cycles, the expected data is visible on the data bus but indicated as ‘invalid’ but
the memory interface controller. The following data is incorrect – the 9 common bits in address and
data do not match anymore. Even after new write cycle has written correct data again, the data read
from the memory is incorrect.+14 Other Responses
Afm Conrtol Using Labview Fpga
Hi, i am naveed, researcher from south korea.
I am working on afm control using labview fpga. I have written a labview code for the generation of point by point triangular wave pattern for my fast axis scan (file attached). Now the problem is that when i saw the commercially available controllers, the wave pattern is a bit different in a sense that the steps are not visible even at very low pixel size of 32. Now my purpose is to generate triangular wave form, point by point in which i should be able to enter my desired number of point i.E pixels. Please guide me in this regard or if you have a vi fulfilling my needs kindly send that to me if possible. Thanks.
Note: can send the code if needed.+4 Other Responses
Pressure Sensor Design And Testing
Looking for some one to design and test a small pressure sensor pcb, that contains the following:
1) igloo nano fpga
criteria: low power, lowest cost, pin migratablility, 1k les to 3k les, non-volatile
2) 5v to 3.3,1.2 v regulators
can bus, power in (5v), power out (5v)
4) mems pressure sensors
criteria: 4 numbers, highest sensitivity, low cost, i2c or other interface to fpga
5) lever driver circuit
shall drive a current of 1a at 5v
6) can driver circuit
shall drive a can bus
giridhar+10 Other Responses