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Recent Logic Devices Inquiries

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Laser Attenuator Optics

We have a pld device and we want to turn it into a heat load machine by purchasing an attenuator. I am having trouble figuring out the specs of the attenuation required. After a few calculations : our laser (248nm - 500mj in 20ns of area 3.9 cm2) we want it to achieve a power per area density of that found in the tokamak (50mw/m2). So the ratio of attenuation defined by the ratio of power densities of pld to tokamak is 1280. Where do we go from here? How do we choose a fixed attenuator? What sort of specs should it have to fit our needs? Thank you! ateam

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    Erik |Senior Process TD Engineer

    I have a PhD in laser spectroscopy and 7 years of experience in laser optics. I am happy to help wit...

    1.8 Hours Later
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    Scott |Corporate Scientist

    So you need to reduce power by a little over 30 dB. I don't understand what the issue is here, just ...

    1.8 Hours Later
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    Kenneth R. |Electro-Physics Scientist/Engineer

    I've been working with lasers, optics, and the like for about 30 years, so have seen pretty much eve...

    2 Hours Later
+5 Other Responses
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Peripheral Component Interconnect Express

Pcie driver to connect ti dsp and altera fpga

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    Richard |

    Hi, I'm afraid S/W is not my area of expertise. Regards, Richard Rooney. ...

    1.2 Hours Later
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    Dimitry |Engineering Director / Consultant

    Hello, we can help you with this project. Our company specialized in HW-SW co-development including ...

    4.9 Hours Later
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    Farhad |Lead HW Design Engineer ASIC/FPGA

    Hi, I am more than happy to answer to any question you have regarding this project. I would like to ...

    1 Day Later
+3 Other Responses
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Fpga

Fpga design ddr3 interface high-speed interfaces altera stratix-v rtl design implementation

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    Kevin |FPGA Design Engineer

    Available and interested please get in touch with me...

    3 Minutes Later
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    Richard |

    Please explain exactly what you need done. I know a company who would provide this kind service on a...

    14 Minutes Later
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    Thomas |Consultant

    I have extensive experience designing digital logic in FPGAs using VHDL and Verilog. I have also wo...

    10.2 Hours Later
+6 Other Responses
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Pressure Sensor Design And Testing

Looking for some one to design and test a small pressure sensor pcb, that contains the following: 1) igloo nano fpga http://www.Microsemi.Com/products/fpga-soc/fpga/igloo-nano criteria: low power, lowest cost, pin migratablility, 1k les to 3k les, non-volatile 2) 5v to 3.3,1.2 v regulators 3) connectors can bus, power in (5v), power out (5v) 4) mems pressure sensors criteria: 4 numbers, highest sensitivity, low cost, i2c or other interface to fpga 5) lever driver circuit shall drive a current of 1a at 5v 6) can driver circuit shall drive a can bus giridhar

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    Pragnesh |Senior Engineer

    Why FPGA? It is usually costly affair then small microcontroller that supports CAN bus....

    5.5 Hours Later
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    Alfredo |Consultant

    No problem in principle, it would help to have a short *****t your project and context. ...

    5.5 Hours Later
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    Al |Zintro Expert

    Giridhar - we'd be interested in discussing this with you. We are experts in FPGA development (a sh...

    5.5 Hours Later
+10 Other Responses
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Fpga

We have a problem of debugging a piece of program running on a custom made xilinx virtex 6 fpga board. This problem related to access external ddr3 sodimm sdram. We need an xilinx fpga export to help solve this problem. Problem details as follows: memory interface problems test setup: a program running on a virtex 6 fpga writes eight sequential data patterns (0 to 511) into different address ranges of an external ddr3 sodimm (“write cycle”). The data pattern and addresses are designed in such way that the lower 9 bits of the data and address match. After all data is written, the data is read back (“read cycle”) in a different order and the least 9 bits of address and data are compared. The core to interface with the sodimm was generated with xilinx mig-tool v3.92. Test results: using chipscope the data and address written into and received from the memory interface is monitored. Write cycle: the data and address written into the memory interface are correct every time. The data and address match from the beginning to the end of each write cycle. Read cycle: at the beginning of the first read cycle the data read from the memory interface is correct. After about 1920 consecutive read cycles, the expected data is visible on the data bus but indicated as ‘invalid’ but the memory interface controller. The following data is incorrect – the 9 common bits in address and data do not match anymore. Even after new write cycle has written correct data again, the data read from the memory is incorrect.

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    Kevin |FPGA Design Engineer

    would love to help. not sure what the process is through zintro - if there's a fee, will ***** ...

    5.3 Hours Later
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    Guillermo |Director

    I manage a small team with a lot of experience in FPGA design, ***** debug. We have worke...

    6.4 Hours Later
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    Farhad |Lead HW Design Engineer ASIC/FPGA

    Solving DDR access problems is aa time consuming and difficult task. We have solved many such proble...

    10.2 Hours Later
+14 Other Responses
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logic semiconductor devices such as complex programmable logic devices (CPLDs) and field-programmable gate arrays (FPGAs)

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